168 search results - page 29 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
A platform that supported Sequential Consistency (SC) for all codes — not only the well-synchronized ones — would simplify the task of programmers. Recently, several hardware ...
136
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DATE
2011
IEEE
14 years 1 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
SIGCOMM
2003
ACM
15 years 2 months ago
2003
ACM
We propose a new objective for network research: to build a fundamentally different sort of network that can assemble itself given high level instructions, reassemble itself as re...
104
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MTV
2006
IEEE
15 years 3 months ago
2006
IEEE
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
108
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ICS
2004
Tsinghua U.
15 years 2 months ago
2004
Tsinghua U.
Studying program behavior is a central component in architectural designs. In this paper, we study and exploit one aspect of program behavior, the behavior repetition, to expedite...