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ISORC
1998
IEEE
15 years 11 months ago
The Time-Triggered Architecture
The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time applicatio...
Hermann Kopetz
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
16 years 21 days ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
WCE
2007
15 years 8 months ago
High-Performance Multigrid Solvers in Reconfigurable Hardware
—Partial Differential Equations (PDEs) play an essential role in modeling real world problems. The broad field of modeling such systems has drawn the researchers’ attention for...
Safaa J. Kasbah, Issam W. Damaj
FUIN
2002
80views more  FUIN 2002»
15 years 6 months ago
P Systems with Replicated Rewriting and Stream X-Machines (Eilenberg Machines)
Abstract. The aim of this paper is to show how the P systems with replicated rewriting can be modeled by X-machines (also called Eilenberg machines). In the first approach, the par...
Joaquin Aguado, Tudor Balanescu, Anthony J. Cowlin...
185
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IPPS
2007
IEEE
16 years 1 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...