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ISPASS
2010
IEEE
15 years 11 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
ISPASS
2009
IEEE
15 years 11 months ago
Differentiating the roles of IR measurement and simulation for power and temperature-aware design
In temperature-aware design, the presence or absence of a heatsink fundamentally changes the thermal behavior with important design implications. In recent years, chip-level infra...
Wei Huang, Kevin Skadron, Sudhanva Gurumurthi, Rob...
ISPASS
2009
IEEE
15 years 11 months ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...
RE
2009
Springer
15 years 10 months ago
[vem: xi: ] - A Methodology for Process Based Requirements Engineering
Service-oriented architectures (SOA) aim at the alignment of business and IT by having a clear business process-centric focus. In order to reach that goal, real-world business pro...
Philipp Liegl, Rainer Schuster, Marco Zapletal, Ch...
EMSOFT
2007
Springer
15 years 10 months ago
Exploiting non-volatile RAM to enhance flash file system performance
Non-volatile RAM (NVRAM) such as PRAM (Phase-change RAM), FeRAM (Ferroelectric RAM), and MRAM (Magnetoresistive RAM) has characteristics of both non-volatile storage and random ac...
In Hwan Doh, Jongmoo Choi, Donghee Lee, Sam H. Noh
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