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117
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PCRCW
1997
Springer
15 years 8 months ago
Power/Performance Trade-offs for Direct Networks
High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As...
Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchil...
114
Voted
PPL
2006
81views more  PPL 2006»
15 years 3 months ago
Microthreading a Model for Distributed Instruction-level Concurrency
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
Chris R. Jesshope
140
Voted
ICCAD
2009
IEEE
113views Hardware» more  ICCAD 2009»
15 years 1 months ago
A performance analytical model for Network-on-Chip with constant service time routers
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
Nikita Nikitin, Jordi Cortadella
134
Voted
IPPS
2007
IEEE
15 years 10 months ago
Scheduling in the Z-Polyhedral Model
The polyhedral model is extensively used for analyses and transformations of regular loop programs, one of the most important being automatic parallelization. The model, however, ...
Gautam Gupta, DaeGon Kim, Sanjay V. Rajopadhye
150
Voted
ASPDAC
2011
ACM
217views Hardware» more  ASPDAC 2011»
14 years 7 months ago
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core syst
This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-cor...
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jants...