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RTAS
2005
IEEE
15 years 9 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
SC
2005
ACM
15 years 9 months ago
Leading Computational Methods on Scalar and Vector HEC Platforms
The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end computing (HEC) platforms, primarily because of their generality, ...
Leonid Oliker, Jonathan Carter, Michael F. Wehner,...
DNA
2004
Springer
132views Bioinformatics» more  DNA 2004»
15 years 9 months ago
Error Free Self-assembly Using Error Prone Tiles
DNA self-assembly is emerging as a key paradigm for nano-technology, nano-computation, and several related disciplines. In nature, DNA self-assembly is often equipped with explicit...
Ho-Lin Chen, Ashish Goel
ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
15 years 9 months ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
SIGCOMM
2003
ACM
15 years 9 months ago
A framework for classifying denial of service attacks
Launching a denial of service (DoS) attack is trivial, but detection and response is a painfully slow and often a manual process. Automatic classification of attacks as single- o...
Alefiya Hussain, John S. Heidemann, Christos Papad...
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