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DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 10 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
201
Voted
DAC
2004
ACM
16 years 7 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
CN
2006
60views more  CN 2006»
15 years 6 months ago
On the efficiency of fluid simulation of networks
Performance evaluation of computer networks through traditional packet-level simulation is becoming increasingly difficult as networks grow in size along different dimensions. Due...
Daniel R. Figueiredo, Benyuan Liu, Yang Guo, James...
DAC
2004
ACM
16 years 7 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
IPPS
2007
IEEE
16 years 21 days ago
Inverse Space-Filling Curve Partitioning of a Global Ocean Model
In this paper, we describe how inverse space-filling curve partitioning is used to increase the simulation rate of a global ocean model. Space-filling curve partitioning allows ...
John M. Dennis