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» Modeling synchronized time series
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ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 5 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 5 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
VTC
2006
IEEE
175views Communications» more  VTC 2006»
15 years 7 months ago
Performance of an Adaptive Multiuser OFDM Uplink with Carrier Frequency Offsets
Using an OFDM based uplink for the future cellular network has been a controversial issue due to difficulties in time and frequency synchronization and high Peak-to-Average Power...
Wei Wang, Tony Ottosson, Tommy Svensson
LCN
2006
IEEE
15 years 7 months ago
Modelling Voice Communication in Disaster Area Scenarios
This paper deals with voice communication models for disaster area scenarios. The goal is to design models that can be used to generate realistic push to talk traffic for single ...
Nils Aschenbruck, Michael Gerharz, Matthias Frank,...
PAMI
2008
182views more  PAMI 2008»
15 years 26 days ago
Gaussian Process Dynamical Models for Human Motion
We introduce Gaussian process dynamical models (GPDMs) for nonlinear time series analysis, with applications to learning models of human pose and motion from high-dimensional motio...
Jack M. Wang, David J. Fleet, Aaron Hertzmann