Sciweavers

2779 search results - page 339 / 556
» Modelling Immunological Memory
Sort
View
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
15 years 8 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
MICRO
1997
IEEE
141views Hardware» more  MICRO 1997»
15 years 8 months ago
Unroll-and-Jam Using Uniformly Generated Sets
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
Steve Carr, Yiping Guan
PODC
1990
ACM
15 years 8 months ago
Self-Stabilization of Dynamic Systems Assuming only Read/Write Atomicity
Three self-stabilizing protocols for distributed systems in the shared memory model are presented. The first protocol is a mutual exclusion protocol for tree structured systems. T...
Shlomi Dolev, Amos Israeli, Shlomo Moran
CF
2007
ACM
15 years 8 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 7 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...