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ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
15 years 8 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...
IJCNN
2006
IEEE
15 years 5 months ago
A Mobile Vision System with Reconfigurable Intelligent Agents
— Performing face detection and tracking on a mobile robot in a dynamic environment is a challenging task with the real-time constraints. To realize a natural reactive behavior o...
Yan Meng
IPPS
2007
IEEE
15 years 6 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
BMCBI
2007
146views more  BMCBI 2007»
14 years 12 months ago
Bayesian hierarchical model for transcriptional module discovery by jointly modeling gene expression and ChIP-chip data
Background: Transcriptional modules (TM) consist of groups of co-regulated genes and transcription factors (TF) regulating their expression. Two high-throughput (HT) experimental ...
Xiangdong Liu, Walter J. Jessen, Siva Sivaganesan,...
DSN
2006
IEEE
15 years 6 months ago
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
Dongkook Park, Chrysostomos Nicopoulos, Jongman Ki...