Sciweavers

96 search results - page 19 / 20
» Module interconnection features in object-oriented developme...
Sort
View
POPL
2000
ACM
15 years 1 months ago
Modular Refinement of Hierarchic Reactive Machines
with existing analysis tools. Modular reasoning principles such as abstraction, compositional refinement, and assume-guarantee reasoning are well understood for architectural hiera...
Rajeev Alur, Radu Grosu
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 1 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
84
Voted
DFN
2009
14 years 10 months ago
MPLS-TP - The New Technology for Packet Transport Networks
: The Internet Engineering Task Force (IETF) and the Telecommunication Standardization Sector of the International Telecommunication Union (ITU-T) have undertaken a joint effort to...
Dieter Beller, Rolf Sperber
BMCBI
2004
101views more  BMCBI 2004»
14 years 9 months ago
A database for G proteins and their interaction with GPCRs
Background: G protein-coupled receptors (GPCRs) transduce signals from extracellular space into the cell, through their interaction with G proteins, which act as switches forming ...
Antigoni L. Elefsinioti, Pantelis G. Bagos, Ioanni...
DCC
2007
IEEE
15 years 9 months ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...