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TCAD
2008
92views more  TCAD 2008»
14 years 9 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
14 years 7 months ago
The synthesis of combinational logic to generate probabilities
As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies suc...
Weikang Qian, Marc D. Riedel, Kia Bazargan, David ...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
15 years 6 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
ICCD
2006
IEEE
96views Hardware» more  ICCD 2006»
15 years 6 months ago
Synthesis of Regular Logic Bricks for Robust IC Design
Kim Yaw Tong, Lawrence T. Pileggi
ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
15 years 6 months ago
Topologically constrained logic synthesis
Subarnarekha Sinha, Alan Mishchenko, Robert K. Bra...