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DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 5 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
CODES
2005
IEEE
15 years 5 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
GECCO
2007
Springer
179views Optimization» more  GECCO 2007»
15 years 5 months ago
A destructive evolutionary process: a pilot implementation
This paper describes the application of evolutionary search to the problem of Flash memory wear-out. The operating parameters of Flash memory are notoriously difficult to determin...
Joe Sullivan, Conor Ryan
TC
2011
14 years 6 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
BIODATAMINING
2008
120views more  BIODATAMINING 2008»
14 years 11 months ago
Filling the gap between biology and computer science
This editorial introduces BioData Mining, a new journal which publishes research articles related to advances in computational methods and techniques for the extraction of useful ...
Jesús S. Aguilar-Ruiz, Jason H. Moore, Mary...