This paper considers the problem of reduced-order observer design. A design procedure is proposed in which the impulse response of the observer is treated as the solution of a gene...
A new discipline, Usability Design, is proposed as an extension to Rational Unified Process (RUP). The aim is to make RUP more user-centred. The discipline springs out of best prac...
With the XC6200 FPGA Xilinx introduced the first commercially available FPGA designed for reconfigurable computing. It has a completely new internal architecture, so new design alg...
Reiner W. Hartenstein, Michael Herz, Frank Gilbert
This paper considers the problem of designing a controller for an unknown plant based on input/output measurements. The new design method we propose is direct (no model identificat...
A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiver is used as a driver example. Compact descrip...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...