395 search results - page 14 / 79 » Multilevel Circuit Partitioning |
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
We propose in this paper a novel framework for multilevel routing considering both routability and performance. The two-stage multilevel framework consists of coarsening followed ...
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
3-D IC has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-on-chip or system-in-package solutions. A cr...
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
CLEIEJ
2010
14 years 7 months ago
2010
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...