395 search results - page 17 / 79 » Multilevel Circuit Partitioning |
PDP
2003
IEEE
15 years 2 months ago
2003
IEEE
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
SC
1995
ACM
15 years 1 months ago
1995
ACM
The design of a parallel implementation of multilevel recursive spectral bisection on the Cray T3D is described. The code is intended to be fast enough to enable dynamic repartiti...
DFT
2008
IEEE
15 years 4 months ago
2008
IEEE
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
ASPDAC
1999
ACM
15 years 2 months ago
1999
ACM
: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into sub...
FPGA
1995
ACM
15 years 1 months ago
1995
ACM
One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning...