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ASPDAC
2000
ACM
117views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Improved algorithms for hypergraph bipartitioning
Multilevel Fiduccia-Mattheyses MLFM hypergraph partitioning 3, 22, 24 is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis 23 , has sinc...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
ICES
2003
Springer
124views Hardware» more  ICES 2003»
15 years 2 months ago
Evolving Multiplier Circuits by Training Set and Training Vector Partitioning
Evolvable Hardware (EHW) has been proposed as a new method for evolving circuits automatically. One of the problems appearing is that only circuits of limited size are evolvable. I...
Jim Torresen
ANTSW
2004
Springer
15 years 1 months ago
Mesh-Partitioning with the Multiple Ant-Colony Algorithm
ed Abstract We present two heuristic mesh-partitioning methods, both of which build on the multiple ant-colony algorithm in order to improve the quality of the mesh partitions. The...
Peter Korosec, Jurij Silc, Borut Robic
69
Voted
DAC
1996
ACM
15 years 1 months ago
Partitioning of VLSI Circuits and Systems
Partitioning plays an increasingly important role in the design process of VLSI circuits and systems. There are partitioning to be solved on all levels of abstraction. The rapidly...
Frank M. Johannes
JPDC
1998
124views more  JPDC 1998»
14 years 9 months ago
Multilevel k-way Partitioning Scheme for Irregular Graphs
In this paper we present a parallel formulation of a multilevel k-way graph partitioning algorithm. A key feature of this parallel formulation is that it is able to achieve a high ...
George Karypis, Vipin Kumar