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VTS
2002
IEEE
106views Hardware» more  VTS 2002»
15 years 2 months ago
How Effective are Compression Codes for Reducing Test Data Volume?
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
Anshuman Chandra, Krishnendu Chakrabarty, Rafael A...
ITC
1999
IEEE
107views Hardware» more  ITC 1999»
15 years 1 months ago
A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
Han Bin Kim, Dong Sam Ha
ASYNC
1998
IEEE
100views Hardware» more  ASYNC 1998»
15 years 1 months ago
An Implicit Method for Hazard-Free Two-Level Logic Minimization
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...
Michael Theobald, Steven M. Nowick
DAC
1996
ACM
15 years 1 months ago
Computing Parametric Yield Adaptively Using Local Linear Models
Abstract A divide-and-conquer algorithm for computing the parametric yield of large analog circuits is presented. The algorithm targets applications whose performance spreads could...
Mien Li, Linda S. Milor
72
Voted
DAC
2005
ACM
14 years 11 months ago
Faster and better global placement by a new transportation algorithm
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
Ulrich Brenner, Markus Struzyna