Synthesis of behaviour models from software development artifacts such as scenario-based descriptions or requirements specifications not only helps significantly reduce the effort...
Automated formal analysis methods such as program verification and synthesis algorithms often suffer from time complexity of their decision procedures and also high space complex...
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
Both parametric design tasks and analysis tasks of technical systems have a similar problem setting: The structure of the system to be configured or analyzed is defined already. W...
VIMS Lab is situated in Department of Computer & Information Sc, University of Delaware, Newark, DE. USA.
At VIMS we work on various problems related to image/video processing...