126 search results - page 7 / 26 » Multiple FPGA Partitioning with Performance Optimization |
DAC
2000
ACM
15 years 10 months ago
2000
ACM
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Transmitting compressed data can reduce inter-processor communication traffic and create new opportunities for DVS (dynamic voltage scaling) in distributed embedded systems. Howe...
FPGA
2009
ACM
15 years 4 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
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HSNMC
2003
Springer
15 years 2 months ago
2003
Springer
Various Internet applications involve multiple parties and usually adopt a one-to-many communication paradigm (multicast). The presence of multiple receivers in a multicast session...
IPPS
1999
IEEE
15 years 1 months ago
1999
IEEE
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...