377 search results - page 20 / 76 » Multiple Instruction Stream Processor |
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Processors that deploy fine-grained reconfigurable fabrics to implement application-specific accelerators ondemand obtained significant attention within the last decade. They tr...
APCSAC
2001
IEEE
15 years 3 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
EUROMICRO
1998
IEEE
15 years 4 months ago
1998
IEEE
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
125
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ASPLOS
2004
ACM
15 years 5 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
101
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CGO
2006
IEEE
15 years 5 months ago
2006
IEEE
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...