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ICPADS
2006
IEEE
15 years 11 months ago
SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Tayl...
CODES
2010
IEEE
15 years 2 months ago
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
Daniel Cordes, Peter Marwedel, Arindam Mallik
ECRTS
2008
IEEE
15 years 11 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
RTAS
2000
IEEE
15 years 8 months ago
An Approach for Supporting Temporal Partitioning and Software Reuse in Integrated Modular Avionics
The Integrated Modular Avionics (IMA) approach can achieve lower overall hardware costs and reduced level of spares by getting multiple applications that have traditionally been i...
Mohamed F. Younis, Mohamed Aboutabl, Daeyoung Kim
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 10 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...