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TC
2011
14 years 4 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
HUC
2007
Springer
15 years 3 months ago
Haggle: Seamless Networking for Mobile Applications
This paper presents Haggle, an architecture for mobile devices that enables seamless network connectivity and application functionality in dynamic mobile environments. Current appl...
Jing Su, James Scott, Pan Hui, Jon Crowcroft, Eyal...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 2 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
15 years 2 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
EUROPAR
2006
Springer
15 years 1 months ago
A One-Stop, Fire-and-(Almost)Forget, Dropping-Off and Rendezvous Point
In order to foster uptake by scientific and business users we need an easy way to access Grid resources. This is the motivation for the A-WARE project. We build upon a fabric layer...
Roger Menday, Björn Hagemeier, Bernd Schuller...