1740 search results - page 38 / 348 » Multiprocessor performance estimation using hybrid simulatio... |
109
click to vote
VLSID
2009
IEEE
16 years 2 months ago
2009
IEEE
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
105
click to vote
CDES
2006
15 years 3 months ago
2006
- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
134
click to vote
JSA
2007
15 years 1 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
128
click to vote
DAC
1997
ACM
15 years 6 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
124
click to vote
ISER
2004
Springer
15 years 7 months ago
2004
Springer
Legged robots display a characteristically periodic motion. Measuring and tracking this motion has traditionally been performed using general inertial measurement techniques. While...