583 search results - page 102 / 117 » NAS Parallel Benchmark Results |
71
Voted
ISVLSI
2008
IEEE
15 years 3 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
98
Voted
CAV
2010
Springer
15 years 1 months ago
2010
Springer
ions of ODE models (MAPLE, GNA). On the algorithmic side (Sec. 3.2), it supports two main streams in high-performance model checking: reachability analysis based on BDDs (symbolic)...
SP
2010
IEEE
14 years 7 months ago
2010
IEEE
A program is defined to be noninterferent if its outputs cannot be influenced by inputs at a higher security level than their own. Various researchers have demonstrated how this pr...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
CODES
2007
IEEE
15 years 3 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...