Sciweavers

75 search results - page 7 / 15
» Near-memory Caching for Improved Energy Consumption
Sort
View
138
Voted
CODES
2011
IEEE
14 years 1 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
14 years 11 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
16 years 2 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
CF
2005
ACM
15 years 3 months ago
Exploiting temporal locality in drowsy cache policies
Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage ...
Salvador Petit, Julio Sahuquillo, Jose M. Such, Da...
MIS
2007
Springer
163views Multimedia» more  MIS 2007»
15 years 1 months ago
Cooperative caching in mobile ad hoc networks based on data utility
Cooperative caching, which allows sharing and coordination of cached data among clients, is a potential technique to improve the data access performance and availability in mobile ...
Narottam Chand, Ramesh C. Joshi, Manoj Misra