983 search results - page 116 / 197 » Negative-Weight Cycle Algorithms |
130
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ICCD
2003
IEEE
15 years 6 months ago
2003
IEEE
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
79
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ISCAS
2003
IEEE
15 years 6 months ago
2003
IEEE
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation meth...
123
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PDP
2003
IEEE
15 years 6 months ago
2003
IEEE
We consider the execution of a complex application on a heterogeneous "grid" computing platform. The complex application consists of a suite of identical, independent pr...
113
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GD
2003
Springer
15 years 6 months ago
2003
Springer
A drawing of a family of cuts of a graph is an augmented drawing of the graph such that every cut in the family is represented by a simple closed curve and vice versa. We show tha...
ITC
2002
IEEE
15 years 5 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...