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129
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SLIP
2006
ACM
15 years 9 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
GECCO
2010
Springer
233views Optimization» more  GECCO 2010»
15 years 8 months ago
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
Jirí Jaros, Vaclav Dvorak
154
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CCGRID
2010
IEEE
15 years 4 months ago
An MPI-Stream Hybrid Programming Model for Computational Clusters
The MPI programming model hides network type and topology from developers, but also allows them to seamlessly distribute a computational job across multiple cores in both an intra ...
Emilio Pasquale Mancini, Gregory Marsh, Dhabaleswa...
ICIP
2002
IEEE
16 years 5 months ago
A no-reference perceptual blur metric
In this paper, we present a no-reference blur metric for images and video. The blur metric is based on the analysis of the spread of the edges in an image. Its perceptual signific...
Frédéric Dufaux, Pina Marziliano, St...
124
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FPL
2004
Springer
141views Hardware» more  FPL 2004»
15 years 9 months ago
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
—This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and...
Zachary K. Baker, Viktor K. Prasanna