Sciweavers

627 search results - page 116 / 126
» Next Generation Architecture for Heterogeneous Embedded Syst...
Sort
View
RTAS
2006
IEEE
15 years 5 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
15 years 5 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
DAC
2003
ACM
15 years 5 months ago
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
LCTRTS
2010
Springer
15 years 6 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
SEMWEB
2009
Springer
15 years 6 months ago
Live Social Semantics
Abstract. Social interactions are one of the key factors to the success of conferences and similar community gatherings. This paper describes a novel application that integrates da...
Harith Alani, Martin Szomszor, Ciro Cattuto, Woute...