69 search results - page 5 / 14 » Noise margin analysis for dynamic logic circuits |
ISQED
2007
IEEE
15 years 3 months ago
2007
IEEE
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
ITC
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
84
Voted
FPT
2005
IEEE
15 years 3 months ago
2005
IEEE
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
111
click to vote
IOLTS
2006
IEEE
15 years 3 months ago
2006
IEEE
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...