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116
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ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
13 years 2 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
LCTRTS
2001
Springer
15 years 5 months ago
A Dynamic Programming Approach to Optimal Integrated Code Generation
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
Christoph W. Keßler, Andrzej Bednarski
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
15 years 9 months ago
Power-Efficient Wakeup Tag Broadcast
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomare...
89
Voted
ICTAI
2007
IEEE
15 years 6 months ago
On Portfolios for Backtracking Search in the Presence of Deadlines
Constraint satisfaction and propositional satisfiability problems are often solved using backtracking search. Previous studies have shown that portfolios of backtracking algorith...
Huayue Wu, Peter van Beek
GLVLSI
1997
IEEE
110views VLSI» more  GLVLSI 1997»
15 years 4 months ago
Algorithm and Hardware Support for Branch Anticipation
Multi-dimensional systems containing nested loops are widely used to model scientific applications such as image processing, geophysical signal processing and fluid dynamics. Ho...
Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Pa...