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» Nonuniform Banking for Reducing Memory Energy Consumption
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ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
15 years 2 months ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
15 years 1 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
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IPPS
2007
IEEE
15 years 4 months ago
An Implementation of Page Allocation Shaping for Energy Efficiency
Main memory in many tera-scale systems requires tens of kilowatts of power. The resulting energy consumption increases system cost and the heat produced reduces reliability. Emerg...
Matthew E. Tolentino, Joseph Turner, Kirk W. Camer...
ISCAS
2007
IEEE
109views Hardware» more  ISCAS 2007»
15 years 4 months ago
Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding
—This paper presents an energy-efficient turbo decoder based on border metric encoding, which is especially suitable for non-binary circular turbo codes. In the proposed method, ...
Ji-Hoon Kim, In-Cheol Park
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
15 years 1 months ago
Cache-Aware Scratchpad Allocation Algorithm
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
Manish Verma, Lars Wehmeyer, Peter Marwedel