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» Nonuniform Banking for Reducing Memory Energy Consumption
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GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
15 years 2 months ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 2 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
ICDE
2005
IEEE
115views Database» more  ICDE 2005»
15 years 11 months ago
Snapshot Queries: Towards Data-Centric Sensor Networks
In this paper we introduce the idea of snapshot queries for energy efficient data acquisition in sensor networks. Network nodes generate models of their surrounding environment th...
Yannis Kotidis
CODES
2006
IEEE
15 years 3 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
CODES
2011
IEEE
13 years 9 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu