Sciweavers

138 search results - page 6 / 28
» Novel architecture for loop acceleration: a case study
Sort
View
DSD
2002
IEEE
88views Hardware» more  DSD 2002»
15 years 2 months ago
The Synthesis of a Hardware Scheduler for Non-Manifest Loops
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
Omar Mansour, Egbert Molenkamp, Thijs Krol
CORR
2010
Springer
101views Education» more  CORR 2010»
14 years 9 months ago
Universal Loop-Free Super-Stabilization
Abstract. We propose an univesal scheme to design loop-free and superstabilizing protocols for constructing spanning trees optimizing any tree metrics (not only those that are isom...
Lélia Blin, Maria Potop-Butucaru, Stephane ...
HPDC
2007
IEEE
15 years 3 months ago
Scaling multiplayer online games using proxy-server replication: a case study of Quake 2
Massively Multiplayer Online Games (MMOGs) are an increasingly popular class of real-time interactive distributed applications that require scalable architectures and parallelizat...
Jens Müller 0004, Sergei Gorlatch, Tobias Sch...
JPDC
2008
108views more  JPDC 2008»
14 years 9 months ago
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
Energy saving is becoming one of the major design issues in processor architectures with multiple functional units (FUs). Nested loops are usually the most critical part in multim...
Meikang Qiu, Edwin Hsing-Mean Sha, Meilin Liu, Man...
IPPS
2009
IEEE
15 years 4 months ago
Exploring FPGAs for accelerating the phylogenetic likelihood function
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological seq...
Nikolaos Alachiotis, Euripides Sotiriades, Apostol...