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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 6 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
134
Voted
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
15 years 6 months ago
Software Versus Hardware Shared-Memory Implementation: A Case Study
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, ...
ASPLOS
1992
ACM
15 years 6 months ago
High Speed Switch Scheduling for Local Area Networks
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...
Thomas E. Anderson, Susan S. Owicki, James B. Saxe...
AOSD
2007
ACM
15 years 6 months ago
Debugging with control-flow breakpoints
Modern source-level debuggers support dynamic breakpoints that are guarded by conditions based on program state. Such breakpoints address situations where a static breakpoint is n...
Rick Chern, Kris De Volder
CASES
2004
ACM
15 years 6 months ago
Providing time- and space- efficient procedure calls for asynchronous software thread integration
Asynchronous Software Thread Integration (ASTI) provides fine-grain concurrency in real-time threads by statically scheduling (integrating) code from primary threads into secondar...
Vasanth Asokan, Alexander G. Dean