2200 search results - page 109 / 440 » Objective reduction using a feature selection technique |
FPGA
2009
ACM
15 years 4 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
ATS
2005
IEEE
15 years 3 months ago
2005
IEEE
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
ACSC
2005
IEEE
15 years 3 months ago
2005
IEEE
The Address Recalculation Pipeline is a hardware architecture designed to reduce the end-to-end latency suffered by immersive Head Mounted Display virtual reality systems. A deman...
NIPS
2007
14 years 11 months ago
2007
Many tasks in speech processing involve classification of long term characteristics of a speech segment such as language, speaker, dialect, or topic. A natural technique for dete...
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ICML
2010
IEEE
14 years 11 months ago
2010
IEEE
We develop an efficient learning framework to construct signal dictionaries for sparse representation by selecting the dictionary columns from multiple candidate bases. By sparse,...