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» Objective reduction using a feature selection technique
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VLSID
2008
IEEE
133views VLSI» more  VLSID 2008»
16 years 4 months ago
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
ICPP
2007
IEEE
15 years 10 months ago
FlexFetch: A History-Aware Scheme for I/O Energy Saving in Mobile Computing
Extension of battery lifetime has always been a major issue for mobile computing. While more and more data are involved in mobile computing, energy consumption caused by I/O opera...
Feng Chen, Song Jiang, Weisong Shi, Weikuan Yu
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
15 years 9 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
CHES
2003
Springer
100views Cryptology» more  CHES 2003»
15 years 9 months ago
Multi-channel Attacks
We introduce multi-channel attacks, i.e., side-channel attacks which utilize multiple side-channels such as power and EM simultaneously. We propose an adversarial model which combi...
Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi
IPPS
1997
IEEE
15 years 8 months ago
Enhancing Software DSM for Compiler-Parallelized Applications
Current parallelizing compilers for message-passing machines only support a limited class of data-parallel applications. One method for eliminating this restriction is to combine ...
Peter J. Keleher, Chau-Wen Tseng