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DAC
2007
ACM
16 years 5 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
1999
ACM
16 years 5 months ago
Memory Exploration for Low Power, Embedded Systems
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
Wen-Tsong Shiue, Chaitali Chakrabarti
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 4 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
ASPDAC
2009
ACM
143views Hardware» more  ASPDAC 2009»
15 years 10 months ago
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or po...
Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai...
WCNC
2008
IEEE
15 years 10 months ago
Joint Power and Bandwidth Allocation in Multihop Wireless Networks
Abstract—This paper considers power and bandwidth allocation to maximize the end-to-end rate in a multihop wireless network. Assuming an orthogonal frequency division multiplexin...
Deqiang Chen, J. Nicholas Laneman