20 search results - page 2 / 4 » On Concurrent Error Detection with Bounded Latency in FSMs |
84
Voted
ASPLOS
2004
ACM
15 years 3 months ago
2004
ACM
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection techniqu...
DFT
2008
IEEE
14 years 11 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
ITC
2000
IEEE
15 years 1 months ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
77
Voted
DAC
2001
ACM
15 years 10 months ago
2001
ACM
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
76
Voted
CHES
2004
Springer
15 years 2 months ago
2004
Springer
Because of the rapidly shrinking dimensions in VLSI, transient and permanent faults arise and will continue to occur in the near future in increasing numbers. Since cryptographic c...