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VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
16 years 1 days ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ET
2002
97views more  ET 2002»
14 years 11 months ago
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
DAC
2008
ACM
16 years 19 days ago
Path smoothing via discrete optimization
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
DATE
2005
IEEE
148views Hardware» more  DATE 2005»
15 years 5 months ago
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits
Multi-channel waveform monitoring technique enhances built-in test and diagnostic capability of mixed-signal VLSI circuits. An 8-channel prototype system incorporates adaptive sam...
Koichiro Noguchi, Makoto Nagata
VTC
2007
IEEE
15 years 6 months ago
Discrete Power Allocation for Lifetime Maximization in Cooperative Networks
Abstract— Discrete power allocation strategies for amplifyand-forward cooperative networks are proposed based on selective relaying methods. The goal of power allocation is to ma...
Wan-Jen Huang, Yao-Win Hong, C. C. Jay Kuo