87 search results - page 12 / 18 » On Discretization of Delays in Timed Automata and Digital Ci... |
84
Voted
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
96
Voted
EMSOFT
2005
Springer
15 years 3 months ago
2005
Springer
Hybrid systems are an appropriate formalism to model embedded systems as they capture the theme of continuous dynamics with discrete control. A simple extension, a network of comm...
73
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
93
Voted
ISPD
2009
ACM
15 years 4 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
74
Voted
ICCD
2005
IEEE
15 years 6 months ago
2005
IEEE
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...