87 search results - page 14 / 18 » On Discretization of Delays in Timed Automata and Digital Ci... |
ICC
2007
IEEE
15 years 1 months ago
2007
IEEE
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
ASYNC
1998
IEEE
15 years 1 months ago
1998
IEEE
Analogue to digital (A-D) converters with a xed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time fo...
107
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CAV
2000
Springer
15 years 1 months ago
2000
Springer
Address: Abstraction, Composition, Symmetry, and a Little Deduction: The Remedies to State Explosion . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A. Pnueli Invited Address...
104
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FPGA
2009
ACM
15 years 2 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
FPGA
2004
ACM
15 years 2 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...