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» On Predictability of Caches for Real-Time Applications
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DAC
2002
ACM
16 years 1 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
102
Voted
CAL
2006
15 years 14 days ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
89
Voted
DAC
2010
ACM
15 years 19 days ago
Performance and power modeling in a multi-programmed multi-core environment
This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-cor...
Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley M...
125
Voted
TVLSI
2008
150views more  TVLSI 2008»
14 years 12 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
JTRES
2009
ACM
15 years 5 months ago
A technology compatibility kit for safety critical Java
Safety Critical Java is a specification being built on top a subset of interfaces from the Real-Time Specification for Java. It is designed to ease development and analysis of s...
Lei Zhao, Daniel Tang, Jan Vitek