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» On Programmable Memory Built-In Self Test Architectures
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MTDT
2002
IEEE
108views Hardware» more  MTDT 2002»
15 years 3 months ago
A Fault Modeling Technique to Test Memory BIST Algorithms
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil ...
126
Voted
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
15 years 2 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...
ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
15 years 2 months ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 2 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
EH
2000
IEEE
81views Hardware» more  EH 2000»
15 years 2 months ago
Toward Self-Repairing and Self-Replicating Hardware: The Embryonics Approach
The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the sour...
Daniel Mange, Moshe Sipper, André Stauffer,...