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» On Structural vs. Functional Testing for Delay Faults
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141
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ASPDAC
2006
ACM
122views Hardware» more  ASPDAC 2006»
15 years 9 months ago
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, ...
125
Voted
DATE
2007
IEEE
155views Hardware» more  DATE 2007»
15 years 10 months ago
Design fault directed test generation for microprocessor validation
Functional validation of modern microprocessors is an important and complex problem. One of the problems in functional validation is the generation of test cases that has higher p...
Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V...
123
Voted
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
15 years 9 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...
143
Voted
TCAD
2008
114views more  TCAD 2008»
15 years 3 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
154
Voted
ET
2002
85views more  ET 2002»
15 years 3 months ago
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
Mehrdad Nourani, Amir Attarha