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59
Voted
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
1 Redundancy removal is an important step in combinational logic optimization. After a redundant wire is removed, other originally redundant wires may become irredundant, and some ...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
ET
2007
14 years 9 months ago
2007
This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a...
GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...