1529 search results - page 15 / 306 » On Timing Analysis of Combinational Circuits |
DAC
2004
ACM
15 years 10 months ago
2004
ACM
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...