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» On Timing Analysis of Combinational Circuits
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TCAD
2008
98views more  TCAD 2008»
14 years 9 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm
CSREAESA
2006
14 years 11 months ago
Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy
- Triple Modular Redundancy is widely used in dependable systems design to ensure high reliability against soft errors. Conventional TMR is effective in protecting sequential circu...
Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wan...
IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
15 years 3 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
ACSAC
2007
IEEE
15 years 4 months ago
Closed-Circuit Unobservable Voice over IP
Among all the security issues in Voice over IP (VoIP) communications, one of the most difficult to achieve is traffic analysis resistance. Indeed, classical approaches provide a...
Carlos Aguilar Melchor, Yves Deswarte, Julien Iguc...
CIBCB
2008
IEEE
15 years 4 months ago
Temporal and structural analysis of biological networks in combination with microarray data
— We introduce a graph-based relational learning approach using graph-rewriting rules for temporal and structural analysis of biological networks changing over time. The analysis...
Chang Hun You, Lawrence B. Holder, Diane J. Cook