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» On Timing Analysis of Combinational Circuits
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ICCAD
2003
IEEE
161views Hardware» more  ICCAD 2003»
15 years 6 months ago
A General S-Domain Hierarchical Network Reduction Algorithm
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
Sheldon X.-D. Tan
ICCAD
2006
IEEE
183views Hardware» more  ICCAD 2006»
15 years 6 months ago
Soft error derating computation in sequential circuits
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
Hossein Asadi, Mehdi Baradaran Tahoori
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
15 years 3 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
ICCAD
2008
IEEE
172views Hardware» more  ICCAD 2008»
15 years 4 months ago
Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis
— Perturbation Projection Vector (PPV) is an established technique for oscillator phase noise analysis; However, the PPV method significantly loses accuracy when circuits have l...
Xiaolue Lai
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
15 years 1 months ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki