1529 search results - page 53 / 306 » On Timing Analysis of Combinational Circuits |
ASPDAC
1999
ACM
15 years 2 months ago
1999
ACM
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
HPCA
2009
IEEE
15 years 4 months ago
2009
IEEE
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...
MICRO
2002
IEEE
14 years 9 months ago
2002
IEEE
There has been much discussion about the best way to combine the benefits of new optical circuit switching technology with the established packet switched Internet. In this paper,...
WCE
2007
14 years 11 months ago
2007
—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-n...