1529 search results - page 54 / 306 » On Timing Analysis of Combinational Circuits |
ICCAD
1998
IEEE
15 years 2 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
FPL
2006
Springer
15 years 1 months ago
2006
Springer
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
DAC
2003
ACM
15 years 3 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
RTSS
2005
IEEE
15 years 3 months ago
2005
IEEE
Static timing analysis safely bounds worst-case execution times to determine if tasks can meet their deadlines in hard real-time systems. However, conventional timing analysis req...
IJCNN
2000
IEEE
15 years 2 months ago
2000
IEEE
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...